1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a CMOS device and a nonvolatile memory which are formed on a silicon semiconductor substrate.
2. Description of the Related Art
Conventionally, the following construction and structure have been used for complementary metal oxide semiconductor (CMOS) transistors, a MOS capacitor, and the like on a silicon semiconductor substrate.
First, as shown in FIG. 3, an NMOS transistor 40, a PMOS transistor 41, and a MOS capacitor 42 are formed on a desired portion of a silicon substrate 28 having a unique surface direction such as <100>or <110>through the application of known technology in which, for example, the NMOS transistor 40 includes a gate oxide film 32 made of a silicon oxide film and a gate electrode 35 made of polysilicon; the PMOS transistor 41 includes a gate oxide film 33 made of a silicon oxide film and a gate electrode 36 made of polysilicon; and the MOS capacitor 42 includes a lower electrode 31, a gate oxide film 34 made of a silicon oxide film, and a gate electrode 37 made of polysilicon on the surface of the silicon substrate 28. In FIG. 3, reference numerals 29, 30, 38 and 39 denote a diffused region for a P-type well, a diffusion region for an N-type well, a source/drain diffused region for the NMOS transistor 40, and a source/drain region for the PMOS transistor 41, respectively.
In each of the formed semiconductor elements such as NMOS transistor 40, PMOS transistor 41, and MOS capacitor 42, the same surface direction is applied to the channel region and the boundary surface between the silicon substrate and the silicon oxide film.
However, in general, the electron mobility is high in the <100> surface, whereas the hole mobility is reduced to one-quarter to one-half of the electron mobility. Further, in the <110> surface, the hole mobility becomes two times higher than that in the <100> surface, but the electron mobility remarkably deteriorates.
That is, when CMOS transistors are formed in the same surface direction, the driving ability of one of the NMOS transistor and the PMOS transistor deteriorates more than that of the other. In order to compensate the deterioration, the channel width of the transistor should be larger, which makes it difficult to miniaturize the transistor.
On the other hand, in order to adapt the CMOS structure without impairing the driving abilities of both NMOS transistor and PMOS transistor, two surface directions exist together in a silicon substrate, and there is adapted the structure in which the NMOS transistor is formed on the <100> surface and the PMOS transistor is formed on the <110> surface (For example, see JP 2005-109498 A and JP 2002-359293 A).
No matter whether in the case of a conventional structure for elements on a unique surface direction, or in the case where different surface directions are applied to an NMOS transistor and a PMOS transistor, the silicon substrate has a uniform and flat surface for a channel surface or a boundary surface of a gate oxide film.
A silicon oxide film formed on the flat surface of the silicon substrate has, however, many crystal distortions or dangling bonds on the boundary surface thereof, which causes the following problems, since the sizes of molecules constituting silicon single crystal and silicon dioxide are different.
1. When a gate oxide film is made much thinner so as to improve the driving ability of a transistor or miniaturize the transistor, influence of the crystal distortions on the boundary surface becomes remarkable, thereby deteriorating the dielectric strength characteristic and reliability of the gate oxide film.
2. Particularly in a MOS capacitor in which the surface of the silicon substrate is mainly used in the accumulation state, or in a tunnel oxide film of a nonvolatile memory, which is used to pass electrons and holes therethrough, the crystal distortion in the boundary surface has more remarkable influence on the characteristics and reliability thereof than those of the gate oxide film of the transistor, thereby making it difficult to miniaturize the semiconductor elements by thinning them.